The present invention relates to a method for detecting the carrier profile of a semiconductor device including a p-n junction portion.
In development of a semiconductor device such as a large scale integrated circuit (referred to as xe2x80x9cLSIxe2x80x9d hereinafter), the most important thing to be done in the initial stage of the development is to accurately and sufficiently grasp or specify the characteristics of transistors in consideration of other elements and devices which are to be integrated together with transistors in a target LSI to be developed. If this is done neither sufficiently nor accurately, and if the characteristic of the transistor can not help being altered due to the change in the later manufacturing process, it would be not rare that there is required a large scale work for modification such as a complex and time consuming work for altering circuits and the others related thereto. Accordingly, the earliest modification of the carrier profile deciding the transistor characteristic has a very important meaning in the initial stage of the development and plays a significant role in shortening theturnaround-time of the development.
Therefore, in order to optimize the carrier profile in the impurity doped region of the transistor such as well, source and drain, lightly-doped-drain (LDD), channel stop depth and so forth, the condition of the method for forming the impurity doped region (for instance, the ion implantation method, the thermal diffusion method, etc.) is examined in general in the initial stage of the development of the device such as LSI. The transistor is then actually manufactured according to the examined and decided condition, and the characteristic of the transistor as manufactured is then examined.
In the examination of the transistor characteristic, it would be not rare to experience that the desk-planned or theoretical characteristic of the transistor differs from that of the actually manufactured transistor. If this happens, it is required to do the work for detecting the actual carrier profile and to compare it with that which is desk-planned, thereby confirming the degree of coincidence or matching between the actual carrier profile and the desk-planned one.
At present, two methods, for instance the secondary ion mass spectrometry (SIMS) and the pulse C-V method are well known and employed in general for detecting the carrier profile of a semiconductor device such as a transistor or like others.
(a) SIMS is a method basically making use of a sputtering phenomenon that occurs on the surface of a test element when irradiating it with primary ions. According to this method, the secondary ions generated in the sputtering phenomenon are analyzed by the mass spectrometer, thereby qualitatively and quantitatively determining the components of the test element. SIMS has the highest detection sensitivity among currently available method for surface analysis and enables an extremely small quantity of the subject matter to be accurately analyzed. Accordingly, SIMS is often used for measuring the impurity profile in the depth direction, for instance, being used for examining the distribution of impurities existing in the depth range of a few microns or so from the surface of the test element. SIMS is usually used for measuring the distribution of impurities existing in the depth range of 100 micrometer or less from the test element surface.
Despite the excellent and preferable performance of the SIMS, however, the scale of equipment for executing SIMS is apt to become larger and at the same time, the operator is required to have a high degree of proficiency in operation of the equipment. Therefore, SIMS might be not always the most preferable method for simply and easily evaluating the impurity or carrier profile of the semiconductor device.
(b) The pulse C-V method is a method in which the C-V characteristic of the oxide film or the p-n junction portion is measured, thereby electrically detecting the carrier profile under the oxide film or in the p-n junction portion. With the pulse C-V method, the carrier profile can be detected with relative ease. However, the pulse C-V method basically directed to the evaluation of the carrier profile at the test element group (TEG) level, so that it might be rather difficult to apply this method to the evaluation of the carrier profile at the device level.
The invention has been made in view of the above-mentioned difficulties and other problems, which were a subject of discussion in the prior art method for detecting the carrier profile. Thus, the object of the invention is to provide a novel and improved method for detecting the carrier profile which can be executed with ease under the less restriction.
In order to solve the above problems, according to the invention, there is provided a method for detecting the carrier profile of a semiconductor device including a p-n junction portion including: a first step of irradiating a p-n junction portion with light rays capable of moving the irradiation position thereof, thereby detecting the relation between the irradiation position and an electromotive force generated in said p-n junction portion being biased with a bias voltage; a second step of detecting the relation between the expanded width of a depletion layer taking place in the p-n junction portion and the bias voltage, based on the relation as detected in the first step; and a third step of detecting a carrier profile in the p-n junction portion, based on the relation as detected in the second step.
According to the method as constituted above, in the second step thereof, the position of the depletion layer edge portion is specified based on the relation detected in the first step, so that there can be detected the relation between the bias voltage and the expanded width of the depletion layer. This is because the magnitude of the optical electromotive force generated by irradiating the depletion layer with light rays differs in general from that which is generated by irradiating the region other than the depletion layer with light rays.
Furthermore, according to the method as constituted above, in the third step thereof, the carrier profile can be detected based on the relation detected in the second step. This is because the expanded width of the depletion layer in the p-n junction portion varies in general depending on the bias voltage and the carrier concentration (activated impurity concentration) in the depletion layer.
As described above, according to the method of the invention, the carrier profile can be detected by measuring the electromotive force generated in the p-n junction portion. To be more advantageous, this measurement can be executed with ease and at a device level.
Furthermore, the first step according to the method of the invention is constituted such that the light ray irradiation is carried out by employing two or more different irradiation angles, thereby detecting the relation between the irradiation position and the electromotive force generated in the p-n junction portion. A point in a space is defined in general as such a point that two straight lines pass therethrough intersecting each other thereat. Therefore, according to the method of the invention, the three-dimensional position of the depletion layer edge portion can be specified by irradiating the p-n junction portion with light rays incident thereon at two or more different irradiation angles.
Still further, the third step according to the method of the invention has such a constitution that the impurity concentration distribution is detected assuming that the p-n junction portion is formed as an abrupt junction. Still further, the third step has such a constitution that the impurity concentration distribution is detected assuming that in the p-n junction portion, the concentration of impurities with the first polarity is made sufficiently higher than that of impurities with the second polarity. Still further, the p-n junction portion is formed by means of the thermal diffusion method, in which impurities having a polarity opposite to that of a semiconductor wafer are doped into the principal surface of the wafer, and the light irradiation in the first step is executed with respect to the principal surface of the wafer.